A trench gate type lateral MOSFET is well known and disclosed in, for example, U.S. Pat. No. 5,723,891 and U.S. Pat. No. 5,640,034. This MOSFET is capable of reducing an on-state resistance by increasing a channel density with a trench gate electrode.
However, in case of a complex IC, a N+ type embedded layer is disposed in a bipolar transistor forming region. As shown in FIG. 11, when the trench gate type lateral MOSFET is formed in a substrate, the N+ type embedded layer 100 provides a drain electric potential. Thus, an electric field is concentrated at a corner of a bottom of a trench gate electrode 108, so that a breakdown voltage is reduced.
A detailed description is explained. In FIG. 11, a silicon island in a N type silicon layer 101 is separated by a trench 102 and an embedded oxide film 103. In the silicon island, a channel forming region 104, a N+ source region 105, a P+ type contact well layer 106, a N+ type drain region 107 and a trench gate electrode 108 are formed. In the silicon island, a N+ type embedded layer 100 is formed on a bottom of the N type silicon layer 101. Here, when the silicon island includes the N+ type embedded layer 100, in a case where a voltage is applied to the N+ type drain region 107, the electric potential of the N+ type embedded layer 100 is also increased in accordance with the drain potential. As a result, the electric field is concentrated at a lower portion of the trench gate electrode 108 disposed on a drain region 107 side (i.e., an XIA portion in FIG. 11), so that the breakdown voltage is reduced. Further, for example, when the N+ embedded layer 100 provides the source electric potential, the electric field is concentrated at an edge of the trench gate electrode 108 (i.e., a corner of the bottom), so that the breakdown voltage is reduced.